http://www.drillingpartss.com » LDMF1GA High temperature memory Introduction LDMF1GA is a high temperature and reliable HAND type and commonly used memory, with fast read and write, high reliability characteristics under high and low temperature and can operate continuously under severe environment of -45℃~175℃. Product model Voltage scope Structure Encapsulation LDMF1GA2.7V~3.6V1G x 8 bitDIP16Characteristics Working temperature scope: -45℃~+175℃ |
The maximum working current: 90mA; standby current: ＜2mA
Power supply voltage Vcc (V): 2.7V~3.6V
Input high level (V): 0.8Vcc~Vcc+0.3
Input low level (V): -0.3~0.2Vcc
Output high level (V):2.4~Vcc
Output low level (V): -0.3~0.4
Encapsulation: 16 PIN DIP lead-free encapsulation (15.5 x 21.6 /2.54 mm space)Pin configurationPin description Pin name Pin function IO0 ～ IO7 Multiplexing I/O Input order, address, input and output data; When chip is not selected or output is invalid, I/O pin is at high impedance state; CLE Command latch enable Enable command is conveyed to register. When CLE is at high level, rising edge of signal, and command through IO port stored into the register.ALE Address latch enable Valid path from enable address to command register. When ALE is at high level, address is latched at the rising edge of.C(—)E(—)Chip enable Component selects control signal. When component is at busy state, high level of C(—)E(—) is ignored; and the component will not return to waiting mode when doing programming or erase operation.R(—)E(—)Read Enable Enable read allows the output of serial data. When the signal is at low level, data is driven to IO port. Data at the falling edge will be valid after R(—)E(—) , and address calculator of internal serial will be increased by 1 automatically.W(—)E(—)Write enable W(—)E(—) inputs write enable to control the input of serial data; Command, address and data latching at the rising edge of W(—)E(—). R/B(—)Ready/Busy output R/B(—) output is used to indicate the operation state of component. When it is at low level, indicating a program, erase or random read is proceeding; when it is at high level, indicating no operation or operation completion, the pin is an open-drain output and will not appear high impedance state when chip is not selected or output unable.Vcc Power supply Vss GroundEncapsulation size and reference picture Product introductionStructure capacity of LDMF1GAEach chip includes 4096 blocks, each block contains 128 pages and each page includes 2112 bytes (2K+64). The programming and reading operation all base on page as unit and erase operation bases on block as unit.
The LDMF1GA data address bys multiplex 8 I/O interfaces. Physical space for 1G byte needs 30 addresses, therefore, 5 cycles required to address: 2 cycles for column address to search the specific position of each page; 3 cycles for row address to search the specific page number of each block. Page writing and programming need 5 same cycles and started after commends input. For erase block operation, only 3 address cycles are needs. Select by writing the commanding into register.
Structure capacity diagram of LDMF1GA Address cycleAddressing IO 0 IO 1 IO 2 IO 3 IO 4 IO 5 IO 6 IO 7 1st cycle A0A1A2A3A4A5A6A7Column adress12nd cycle A8A9A10A110000Column adress23rd cycle A12A13A14A15A16A17A18A19Row address 14th cycle A20A21A22A23A24A25A26A27Row address 25th cycle A28A29A3000000Row address 3Command listFunction 1st cycle 2nd cycle Reset FFh-Read 00h30hPage programming 80h10hBlock erase 60hD0h
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